I’ll explain myself. I’m doing a small project using a few dependencies, so I have to add them when I call gcc. Everything else is really easy. I just have c files and header files. I find it really cumbersome to have to tell make what headers go with what c files when they have the same name. I don’t see why we don’t have a build system where you simply have to give a project folder with the name of source file with the main() function, give the name of the output executable, the external dependecies to be called with gcc, and that’s it. Everything else can be automatically detected and linked apropriately, even with multiple folders inside the project folder. Does something like that exist that’s simple to use, or is this doable in make?
There’s a lot of tricks you can use in Makefiles. I recommend reading the infopages
info make
. If your.c
and.h
files really have the same name, you should be able to get away with this rule%.c: %.h
, but it is worth it to read the infopages.Also worth mentioning is
gcc -MM filename.c
which will generate a Makefile rule with the (non-system) headers included infilename.c
.Good luck with you project!